In System Reflow of Low Temperature Eutectic Bond Balls

ABSTRACT

Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of, and claims priority under 35U.S.C. §120 from, nonprovisional U.S. patent application Ser. No.12/798,132 entitled “In System Reflow of Low Temperature Eutectic BondBalls,” filed on Mar. 30, 2010, the subject matter of which isincorporated herein by reference.

TECHNICAL FIELD

The present disclosure generally relates to in system reflow of bondballs, and more specifically to affixing a semiconductor substrate to aprinted circuit board with low temperature eutectic bond balls.

BACKGROUND INFORMATION

The current state of the art of semiconductor development is the massproduction of large integrated circuits “IC's” containing severalmillion active components. One type of device fitting this descriptionis a large Field Programmable Gate Array “FPGA.” FPGAs and other devicesmay operate at speeds of several hundred Megahertz and it is not unusualthat these integrated circuits include over a thousand pins that bringhigh speed signals into and out of the integrated circuit die. With alarge number of active internal components switching at high speeds,these devices consume large amounts of power. Therefore, it is necessaryto have a packaging solution that allows for the distribution of over athousand high speed signal lines and also provides for a plurality ofconnections to supply power to the device. To solve this problem for asingle FPGA, IC designers have used a technique wherein thousands of“bumps” are distributed over the surface of the FPGA via thick metallines. It would not be unusual to have two-thousand bumps for power andanother two thousand for ground. The large number of bumps reserved forpower ensures only a minimal resistive drop from the surface of thedevice to the active devices within the FPGA.

The power and signal connections extend from the bumps present on thesurface of the FPGA to balls of a Ball-Grid-Array “BGA” package. A BGAutilized for packaging a large FPGA has approximately 1500 balls; 1000for input and output “I/O” connections and 500 for power and groundconnections. Power is supplied to the balls of the BGA package throughthick metal conductors to the bumps present on the surface of the FPGA.A drawing of a BGA package is shown in FIG. 1 (Prior Art). A pluralityof bond bumps 3 are shown disposed between FPGA die 5 and package PCB 1.Array of bond balls 2 are shown attached to a lower surface of thepackage PCB 1 and are coupled to bond bumps 3 of FPGA die 5 withconductors within the PCB (not shown). The array of bond balls 2 areused to connect the BGA package to a system containing several similardevices and other components. Bond bumps 3 are attached to solderreflowable bond pads (not shown) on the package PCB 1. The bond pads arethen connected layers of interconnect metal within the package PCB. Thebond bumps 3 and bond pads are made of materials selected to providesufficient electrical and mechanical contact between FPGA integratedcircuit die 5 and the package PCB 1. For instance bond bumps 3 may bemade of an alloy containing tin and lead. The package PCB may be an FR4type circuit board constructed of woven glass and epoxy. Because theFPGA die may consume large amounts of power during operation, themechanical connection will be subjected to stress and potentialelectrical failure from temperature changes caused by power dissipationin the FPGA die and other devices. For example, the coefficient oflinear thermal expansion for the FR4 type PCB 1 is approximately elevenparts per million per degree Centigrade “ppm/° C.” The same coefficientfor silicon of the FPGA die is three ppm/° C. Because of this disparity,it is possible for the linear expansion to cause electrical conductorsin FPGA die 5 to delaminate from the silicon substrate of FPGA die 5.Furthermore, thermal cycling may cause grain growth in bond bumps 3 andmay increase the likelihood of voids and cracks developing within bondbumps 3. The presence of voids or cracks is likely to cause a decreasein electrical conductivity or failure of continued electrical andmechanical contact between FPGA die 5 and package printed circuit board1.

In an electrical system containing several FPGA die and othercomponents, multiple levels of assembly may be required. The BGA packageof FIG. 1 and other devices may be assembled to a larger system-levelprinted circuit board which may further be a component of an even largersystem. To interconnect each level of assembly, the system temperatureis increased to the melting point of the solder balls or solder bumpsbetween components. Repeated high temperature cycling of the componentscan fatigue the materials present in the PCB's. One approach to solvethis problem is to lower the temperature by providing a solder ball witha lower melting point. U.S. Pat. No. 6,379,982 discloses one of thesestructures and is shown in FIG. 2.

FIG. 2 is a cross-sectional drawing of a solder ball 13, a low meltingpoint metal layer 11, bond pad 12, integrated circuit “IC” chipinterconnect 16, and substrate 15. Solder ball 13 is a reflowed highmelt (ninety-seven percent lead and three percent tin) solder ball thatis positioned above bond bad 12. Bond pad 12 is a solder wettable padthat makes contact through a via to IC chip interconnect 16 which is acopper trace disposed within conventional substrate 15 and covered bypassivation layer 17. Low melting point layer 11 is a low melting pointmetal such as tin, bismuth, indium, or alloys of these materials and isdisposed upon solder ball 13. When the interconnect structure of FIG. 2is subjected to a low temperature joining cycle, a volume of eutecticalloy is formed atop the solder ball 13. When subjected to additionaleutectic temperature cycles, the volume of eutectic alloy melts andforms a structure with improved thermal fatigue resistance and alsoallows for easy removal of the IC chip for the purpose of testing orreplacement.

A semiconductor substrate has also been invented as a solution tofailures caused by devices manufactured on substrate materials withdisparate coefficients of linear expansion and is shown in FIG. 3. FIG.3 shows a semiconductor substrate 9 and a plurality of FPGA dice 5-8disposed on semiconductor substrate 9. Arrays of bond bumps 3 aredisposed between FPGA dice 5-9 and semiconductor substrate 9. The bondbumps 3 mechanically and electrically connect FPGA dice 5-9 tosemiconductor substrate 9. Because the FPGA die and the semiconductorsubstrate 9 are both capable of being constructed from a siliconsubstrate, the coefficients of linear expansion are approximately equal.Thus the likelihood of failure caused by materials having disparatecoefficients of linear expansion is reduced.

FIG. 4 is a cross-sectional drawing of the semiconductor substrate 9 ofFIG. 3. An interconnect structure 20 containing a “thin conductor layersportion” 22 characterized as having a plurality of thin fine-pitchconductors is disposed onto a “power connection structure” 30. Aplurality of thick horizontal conductors is disposed within a “thickconductor layers portion” 31 within power connection structure 30 and aplurality of through-holes extends vertically through a semiconductorpower through-hole portion 32 within the power connection structure 30.These thick horizontal conductors present within the power connectionstructure 30 are of a thickness of approximately two microns or greater.A conductive via is disposed within each through-hole. An example of athrough-hole containing a conductive via 33 is shown disposed within thesemiconductor power through-hole portion 32. A plurality of bondingbumps 3 is disposed upon the thin conductor layers portion 22. The bondbumps are arrayed to match the corresponding array of die bond pads 24present on the FPGA dice 5-8 of FIG. 3. The bond bumps conduct power tothe FPGA dice through vertical vias within through-holes of the powerconnection structure 30 to thick horizontal conductive layers presentwithin the thick conductor layers portion 31. The thick conductor layersare then electrically coupled to a thick conductor layer present on thebottom plane of the semiconductor power through-hole portion by theconductive vias disposed within the semiconductor power through-holeportion 32. In this manner, a large amount of current required by theFPGA devices is conducted vertically through the power connectionstructure 30 to thick conductors within the thick conductor layersportion 31 to vias extending through the interconnect structure 20 tothe bond pads 24 and then to bond bumps 23 that interface to the powerconnections on the surface of FPGA dice 5-8 of FIG. 3. This provides forlow resistance power connections through the substrate whilesimultaneously allowing the maximum density of thin fine-pitch conductorinterconnects within the interconnect structure 20 for routing signalsbetween the plurality of FPGA dice 5-8 of FIG. 3 disposed onsemiconductor substrate 9.

The semiconductor substrate 9 of FIG. 4 may be constructed by couplingportions manufactured by disparate processing techniques. For example,thin conductor layers portion 22 may be constructed by traditionalwet-etch processing methods. Furthermore, power connection structure 30may be processed using traditional dry-etch processing methods. Oncethin conductor layers portion and thick conductor layers portion 32 areprocessed they can be joined together by fusion bonding the twostructures. Fusion bonding permits the planar surfaces of interconnectstructure 20 and power connection structure 30 to contact each otherphysically within atomic dimensions such that direct bonds exist betweenthe two structures obviating any need for adhesive material between thetwo structures. In other embodiments, interconnect structure 20 andpower connection structure 30 are connected through the use of adhesivematerials between the structures.

The semiconductor substrate 9 supports routing signal connectionsbetween a plurality of semiconductor ICs with thin, fine-pitchconductors and conduction of power to the semiconductor ICs throughthick conductors with large feature sizes. However, it is necessary tomake power connections to the semiconductor substrate 9. It is alsonecessary to route signals to and from FPGA dice 5-9 from othercomponents not located on the same semiconductor substrate. One methodof making power connections and signal connections to the semiconductorsubstrate is with Shin-Etsu conductive elastomeric connectors fromShin-etsu Polymer Co., Ltd. However, these connectors have a higherprofile than solder balls, cost more to manufacture than solder balls,and are not as fine in pitch as those allowed with solder ballinterconnections. Another possible method of making power connections isto connect large copper bus bars to the backside of the semiconductorsubstrate 9. However, a large thick bar of copper has disparatecoefficients of linear expansion compared to semiconductor substrate 9and thus delamination of the copper layers of power connection structure30 from semiconductor substrate 9 may occur. Furthermore, asemiconductor substrate is not a suitable substrate for supporting themultiple types of components that are also part of the system. Thesecomponents include: fiber-optic connectors, crystal oscillators, voltageregulators, and other types of components and connectors. In addition,the aforementioned connections means are not easily removed withoutdestroying the semiconductor substrate if semiconductor substrate 9requires rework or additional testing.

A substrate capable of connection to a semiconductor substrate istherefore desired which allows 1) robust mechanical and electricalconnection; 2) interfacing to thousands of high density IC chipinterconnections; 3) low resistance conductors capable of supportinghigh current, power connections; 4) mounting of physical connectors anda variety of electrical components; and 5) nondestructive detachment fortest or qualification of the semiconductor substrate.

SUMMARY

Bond ball cracks and voids formed by repeated thermo-mechanicallyinduced stresses are a major source of failure in Ball Grid Arrayattached semiconductor devices. Low temperature bond balls connect twostructures having disparate coefficients of linear thermal expansion.After assembly, and during a scheduled maintenance period in normaloperation, an integrated circuit is made to heat the device such thatthe low temperature bond balls melt and heal any cracks or voids thatmay have previously formed. Low temperature bond balls connect twostructures having disparate coefficients of linear thermal expansion. Anintegrated circuit is made to heat the device such that the lowtemperature bond balls melt. After melting, the bond balls solidify, andthe device is operated with the bond balls solidified.

In one example, one of the two structures is a semiconductor substrate,and the other structure is a printed circuit board. The integratedcircuit is a Field Programmable Gate Array (FPGA) die mounted to thesemiconductor substrate. The bond balls include at least five percentindium. The FPGA is loaded with a bit stream. The bit stream configuresthe FPGA such that the FPGA has increased power dissipation, which meltsthe balls. After the melting, a second bit stream is loaded into theFPGA and the FPGA is operated in a normal user-mode using the second bitstream.

Further details and embodiments and methods are described in thedetailed description below. This summary does not purport to define theinvention. The invention is defined by the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, where like numerals indicate like components,illustrate embodiments of the invention.

FIG. 1 (Prior Art) is a cross-sectional diagram of a Ball-Grid-Array“BGA” package containing an Field Programmable Gate Array FPGA mountedto a package “Printed Circuit Board” PCB.

FIG. 2 (Prior Art) is a cross-sectional diagram illustrating a lowmelting point metal layer disposed onto a solder ball.

FIG. 3 is a perspective view of a plurality of FPGA dice mounted upon asemiconductor substrate.

FIG. 4 is a cross-sectional diagram of the semiconductor substrate ofFIG. 3 with an interconnect structure adhered to a power connectionstructure and showing a plurality of through-holes disposed within thepower connection structure.

FIG. 5 is a perspective view of a semiconductor substrate mounted upon aPrinted Circuit Board “PCB” with low temperature bond balls disposedbetween the semiconductor substrate and the PCB and wherein FPGAscontaining reflow control circuits in accordance with one novel aspect.

FIG. 6 is a cross sectional diagram of a Printed Circuit Board “PCB”disposed between two semiconductor substrates and wherein lowtemperature bond balls attach the semiconductor substrates to the PCB.

FIG. 7 is a cross-sectional diagram of an FPGA with reflow controlcircuit, a semiconductor substrate, and printed circuit board andwherein the FPGA causes the low temperature bond balls to melt inaccordance with one novel aspect.

FIG. 8 is a cross-sectional diagram of an FPGA with reflow controlcircuit, a semiconductor substrate, and printed circuit board andwherein the FPGA is configured with a second bit-stream and the lowtemperature bond balls are not melted.

FIG. 9 is a top-down view of a Printed Circuit Board “PCB” containingtwo semiconductor substrates also showing a variety of electricalcomponents and connectors disposed on the PCB.

FIG. 10 is a cross-sectional diagram showing a low temperature bond ballin electrical and physical contact with printed circuit boardinterconnect in accordance with another novel aspect.

FIG. 11 is a cross-sectional diagram showing a low melting point metallayer disposed onto a Printed Circuit Board “PCB” in electrical andphysical contact with a solder ball of a semiconductor substrate thatmay be used in a system with FPGAs and reflow circuits in accordancewith yet another novel aspect.

FIG. 12 is a cross-sectional diagram showing a low melting point metallayer disposed onto an unreflowed solder ball of a semiconductorsubstrate that may be used in a system with FPGAs with reflow circuitsin accordance with one novel aspect.

FIG. 13 is a cross-sectional diagram showing a semiconductor substrate,FPGA integrated circuit dice with reflow circuits, and a Printed CircuitBoard “PCB” wherein the PCB has wells for receiving bond balls inaccordance with another novel aspect.

FIG. 14 is a flowchart of a novel method of reflowing bond balls byloading FPGAs with multiple bit-stream patterns.

DETAILED DESCRIPTION

FIG. 5 is a perspective view of a semiconductor substrate 40 mountedupon a Printed Circuit Board “PCB” 50. Also shown in FIG. 5 are FieldProgrammable Gate Array “FPGA” dice 41-44, reflow control circuits 101,bond bumps 45, and low temperature bond balls 72. FPGA dice 41-44 arecustomer configurable integrated circuits disposed upon the top surfaceof semiconductor substrate 40. Bond bumps 45 are arrays of solder bumpsthat are used to electrically and mechanically connect FPGA dice 41-44to semiconductor substrate 40. Each array of bond bumps 45 are disposedbetween die bond pads (not shown) on the underside of each FPGA die andbond pads (not shown) on the top surface of semiconductor substrate 40.Bond bumps 45 are solder bumps made of approximately five percent tinalloyed with lead and are selected to provide reliable mechanical andelectrical connection between the corresponding bond pads of the FPGAdice and semiconductor substrate. In other embodiments, the FPGA diceand semiconductor substrate are mechanically and electrically connectedby bond bumps that do not contain lead or lead alloy. Semiconductorsubstrate 40 is a structure that supports routing thousands of thinfine-pitch conductors between FPGA dice 41-44 and thick horizontalconductors necessary for making power connections to FPGA dice 41-44.Semiconductor substrate 40 may have a plurality of through-holesextending vertically through semiconductor substrate 40 and may beconstructed by coupling portions manufactured by disparate processingtechniques. For example, the portion containing the thin fine-pitchconductors may be constructed by traditional wet-etch processing methodsand the portion containing the thick horizontal conductors may beprocessed using traditional dry-etch processing methods. Adhesivematerials may be used to join these portions or alternatively they maybe fusion-bonded together.

Printed Circuit Board “PCB” 50 is used to mechanically and electricallyconnect semiconductor substrate 40 and other components (not shown) andmay be an FR4 type circuit board constructed of woven glass and epoxy.Low temperature bond balls 72 are shown disposed between semiconductorsubstrate 40 and PCB 50. Each low temperature bond ball 72 is disposedbetween a bond pad (not shown) on the underside of semiconductorsubstrate 40 and a bond pad (not shown) on the top surface of PCB 50.Low temperature bond balls 72 mechanically and electrically connectsemiconductor substrate 40 to PCB 50. Low temperature bond balls may bemade by screening a low melting point eutectic solder paste onto asurface of PCB 50 and subsequently heating to obtain a solder ballprofile approximately three-hundred microns in diameter. Low meltingpoint eutectic solder pastes may be made of low melting point alloyssuch as Indalloy 77 from Indium Corporation of Utica, N.Y. Indalloy 77is an alloy of approximately ninety-five percent Gallium and fivepercent Indium and has liquidus and solidus temperatures of twenty-fivedegrees centigrade and sixteen degrees centigrade, respectively. To forma mechanical and electrical connection between the semiconductorsubstrate 40 and PCB 50, the low temperature bond balls 72 must bemelted and then solidified. In order to reflow or melt the lowtemperature bond balls 72, the temperature must be raised approximatelytwenty degrees centigrade above the liquidus temperature for a durationof approximately thirty seconds. Subsequent cooling causes formation ofa fine-grained metallic solid bond ball structure.

Reflow control circuit 101 may be an electronic circuit in FPGA dice41-44. Reflow control circuit 101 controls the temperature the FPGA dice41-44 and semiconductor substrate 40. Increasing the temperature of theFPGA dice 41-44 and semiconductor substrate 40 above the liquidustemperature of the low temperature solder balls 72 causes the balls toreflow. Subsequent cooling of the melted low temperature solder balls 72causes the balls to solidify. In one embodiment, the reflow controlcircuit determines when reflow or melting of the low temperature bondballs is necessary and causes the FPGA dice 41-44 to operate attemperatures above the liquidus temperature of the low temperature bondballs 72. The increased temperature of FPGAs 41-44 raise the temperatureof the attached semiconductor substrate past the liquidus temperature ofthe low temperature bond balls which subsequently causes the lowtemperature bond balls 72 to melt. The reflow control circuit 101subsequently causes the temperature of FPGAs 41-44 to decrease below thesolidus temperature and bond balls 72 solidify. Melting the lowtemperature bond balls and then solidifying produces a fine grained bondbetween semiconductor substrate 40 and PCB 50. In another embodiment,operation of FPGAs 41-44 changes the temperature of semiconductorsubstrate 40 and low temperature bond balls 72 because reflow controlcircuit 101 controls operation of a cooling fan. In yet anotherembodiment, operation of FPGAs 41-44 changes the temperature ofsemiconductor substrate 40 and low temperature bond balls 72 becausereflow control circuit 101 controls circulation of a coolant fluidsurrounding the semiconductor substrate 40. Other embodiments of theinvention require a single reflow control circuit 101 instead ofmultiple reflow control circuits. In other embodiments the reflowcontrol circuit is not within the FPGA.

Semiconductor substrates may be mounted on both sides of a printedcircuit board. FIG. 6 is a cross sectional diagram of a printed circuitboard “PCB” 50 disposed between two semiconductor substrates 40 and 51.Memory integrated circuit dice 74, 78 and FPGA dice 41, 42 are shownattached to one surface of semiconductor substrate 40 by arrays of bondbumps 45. Semiconductor substrate 40 has interconnect layers (not shown)that route interconnect power connections to memory die 74, 78 and FPGAdie 41, 42. Semiconductor substrate 40 is mounted to a top surface ofPCB 50. Low temperature bond balls 72 are disposed between semiconductorsubstrate 40 and PCB 50 and mechanically and electrically connectsemiconductor substrate 40 and PCB 50. Fiber-optic connectors 151, 152and other components (not shown) are attached to one surface of PCB 50.It is possible to bring a signal from outside PCB 50 onto PCB 50 usingfiber-optic connectors 151, 152 or other components. For instance, anoptical signal could be received by fiber-optic connector 151 andtransmitted to FPGA die 42. The optical signal is received byfiber-optic connector 151 and is converted to an signal which is routedto FPGA die 42 via interconnects within PCB 50, low temperature bondballs 72, interconnect lines (not shown) within semiconductor substrate40, and bond bumps 45.

Semiconductor substrate 51 is attached to another surface of PCB 50 bylow temperature bond balls 72. Semiconductor substrate 51 contains FPGAdice 52, 53 and memory integrated circuit dice 172, 173. Arrays of bondbumps 45 electrically and mechanically connect FPGA die 51, 52 andmemory die 172, 173 to semiconductor substrate 51. Fiber-opticconnectors 170, 171 are mounted to another surface of PCB 50 andsimilarly connect signals from off of PCB 50 to components attached tosemiconductor substrate 51. Signals from components on semiconductorsubstrate 51 can be routed to components on semiconductor substrate 40via bond bumps 45 on the bottom surface of semiconductor substrate 51,interconnect lines within semiconductor substrate 51 (not shown), lowtemperature bond balls 72 mounted on the lower surface of PCB 50,through interconnects (not shown) of PCB 50 to low temperature bondballs 72 on the top surface of PCB 50 through interconnect lines ofsemiconductor substrate 40 and bond bumps 45 on the top surface ofsemiconductor substrate 40 to components on semiconductor substrate 40.

When low temperature bond balls 72 are melted, surface tension of theliquefied metal holds semiconductor substrates 40 and 51 in alignmentwith PCB 50. In some embodiments it may be desirable to providealignment structures to hold semiconductor substrates 40, 51 inalignment with PCB 50 while melted low temperature bond balls 72solidify. FIG. 6 contains alignment structures 90, 91, 161, and 162.Alignment structures 90, 91 are attached to the top surface of PCB 50and protrude into corresponding tapered cavities of semiconductorsubstrate 40. Alignment structures 161, 162 are similarly attached tothe bottom surface of PCB 50 and protrude into corresponding taperedcavities of semiconductor substrate 51. Alignment structures can 90, 91,161, 162 can be attached to PCB 50 using adhesives and the correspondingtapers can be drilled or etched into the respective semiconductorsubstrates. As melted low temperature bond balls 72 solidify, alignmentstructures 90, 91, 161, and 162, guide semiconductor substrates 40 and51 into alignment with PCB 50. In other embodiments the alignmentstructures and matching cavities are not tapered.

FIG. 7 is a cross-sectional diagram of an FPGA integrated circuit die41, a semiconductor substrate 40, and a PCB 50. FPGA integrated circuitdie 41 includes a reflow control circuit 101 and logic gates 105. Anarray of bond bumps 45 mechanically connects FPGA die 41 tosemiconductor substrate 40. An array of low temperature bond balls 72are shown disposed between semiconductor substrate 40 and PCB 50. Thelow temperature bond balls 72 electrically and mechanically connectsemiconductor substrate 40 and PCB 50. FPGA die 41 contains a reflowcontrol circuit 101 and a plurality of logic gates 105. Reflow controlcircuit 101 includes timer circuit 102, temperature sensor 103, andcontrol circuit 104. In one novel aspect, timer circuit 102 determinesthe maximum time duration between reflows and sends a signal to controlcircuit 104. Control circuit 104 receives the signal and causes the FPGAdie 41 to load a first bit-stream 107. The first bit-stream 107 isstored in memory within FPGA die 41. In other embodiments, firstbit-stream 107 is loaded from external memory or sources external toFPGA die 41. First bit-stream 107 is loaded into logic gates 105 andcauses higher speed operation of FPGA die 41 which causes thetemperature of FPGA die 41 to increase. Bit-stream 107 causes increasedpower dissipation by switching the plurality of logic gates 105. Thetemperature of the FPGA die is measured by temp sensor 103. Thetemperature of FPGA die 103 eventually exceeds the liquidus temperatureof low temperature bond balls 72. The heat is conducted from the FPGAdie, through bond bumps 45, and semiconductor substrate 40 to lowtemperature bond balls 72. Low temperature bond balls subsequently meltand may remove voids in the bond balls caused by temperature fatigue.Control circuit 104 may also regulate the rate of increase oftemperature. When control circuit 104 receives a signal from thetemperature sensor 103 indicating a temperature sufficient to melt lowtemperature bond balls 72, control circuit 104 sends a signal to timercircuit 102 enabling the timer circuit to count the duration of reflow.Once the timer circuit 103 indicates reflow duration is complete, thecontrol circuit 104 resets timer circuit 102 and loads a secondbit-stream into logic gates 105 which allows the FPGA die 41 to enter anormal operating mode. FPGA die 41, semiconductor substrate 40, and lowtemperature bond balls 72 subsequently cool to less than the solidustemperature of low temperature bond balls 72.

In alternative embodiments, control circuit 104 loads a bit-stream thatdoes not cause higher speed operation but instead causes more of logicgates 105 to switch and dissipate heat energy. In yet anotherembodiment, control circuit 104 enables or disables a system fan (notshown) in order to raise or lower the temperature of FPGA die 41,semiconductor substrate 40, and low temperature bond balls 72. In yetanother embodiment, the control circuit 104 is able to regulate the flowof coolant fluid in the system to control temperatures.

In another embodiment, the low temperature bond balls 72 may allownondestructive detachment of semiconductor substrate 40 from PCB 50during test or qualification. After the testing of semiconductorsubstrate 40 is complete, the bond balls 72 are heated until they melt.After melting, power is removed from semiconductor substrate 40 and thesemiconductor substrate is removed from PCB 50 before the melted bondballs 72 solidify. In some embodiments a Light Emitting Diode (“LED”) isused to indicate when bond balls 72 are in their melted state and as asignal to disconnect power from semiconductor substrate 40.

FIG. 8 is a cross-sectional diagram of the system in FIG. 7 but with asecond bit-stream 110 being loaded into plurality of logic gates 105 ofFPGA die 41. In this drawing, the low temperature bond balls are solidand timer circuit 102 has been reset and is counting the duration untilthe next “reflow” cycle when the low temperature balls 72 will be meltedand subsequently solidified. The subsequent melting and cooling cyclesmay remove voids and large-grain structures in bond balls 72 and improvefatigue resistance of bond balls 72. In other embodiments, controlcircuit 104 will cause the low temperature bond balls 72 to melt after afailure in the system has been detected.

FIG. 9 is a perspective view of a Printed Circuit Board “PCB” 50including two semiconductor substrates 40, 51 and a variety ofelectrical components and connectors disposed on the PCB 50.Semiconductor substrate 40 includes FPGA dice 41-44, memory dice 80-87,and alignment structures 94-97. Semiconductor substrate 51 includes FPGAdice 52-55, memory dice 71-78, and alignment structures 90-93. PCB 50includes fiber-optic connectors 120-123, fiber-optic connectors 150-153,power regulators 125-132, and Crystal Oscillators “XTAL” 135-138. Thesecomponents may be traditionally mounted on printed circuit boardsubstrates. Furthermore, these components may also be required tointerface or operate with components mounted onto semiconductorsubstrates 40, 51. Because signals from components on the PCB 50 can berouted on interconnect lines (not shown) in PCB 50 to components onsemiconductor substrates 40, 51 it is not necessary to mount thesecomponents on semiconductor substrates 40, 51.

FIG. 10 is a cross-sectional diagram showing a low temperature bond ball233 in electrical and physical contact with an interconnect layer 245 ofPCB 50. Low temperature bond ball 233 may be one of Low Temperature bondballs 72 of FIG. 7. FIG. 10 includes semiconductor substrate 40,semiconductor substrate interconnect 231, passivation layer 232, bondpad 234, low temperature bond ball 233, and printed circuit boardinterconnect 245 of PCB 50. Semiconductor substrate 40 is a circuitboard constructed from a silicon substrate. Semiconductor substrate 40includes semiconductor substrate interconnect 231, a metal interconnectthat may include copper. Passivation layer 232 is shown on the bottomsurface of semiconductor substrate 40. Passivation layer 232 is anon-conductive material coating on semiconductor substrate 232 thatprevents reflowed solder balls from electrically short-circuitinginterconnect lines and bond pads. PCB 50 may be an FR4 type circuitboard with printed circuit board interconnect 245 that may includecopper. Low temperature bond ball 233 is shown disposed betweensubstrate 40, and a PCB 50. Low temperature bond ball 233 may bethree-hundred microns in diameter and made of a metal selected from agroup comprising bismuth, indium, tin, or alloys thereof.

FIG. 11 is a cross-sectional diagram showing an unreflowed solder ball238 in electrical and physical contact with a layer of low melting pointmetal 240. This structure of FIG. 11 may also be used in the system ofFIG. 7. Low melting point metal layer 240 is in electrical and physicalcontact with an interconnect layer 245 of a PCB 50. FIG. 11 alsoincludes a semiconductor substrate 40, semiconductor substrateinterconnect 231, passivation layer 232 and bond pad 234. Semiconductorsubstrate 40 includes a semiconductor substrate interconnect 231 whichis a metal interconnect that may include copper. Passivation layer 232is shown on the bottom surface of semiconductor substrate 40. Printedcircuit board interconnect 245 is disposed within PCB and may includecopper. Solder ball 238 is shown disposed between bond pad 234 and lowmelting point metal layer 240. Low melting point metal layer 240 is ametal selected from a group comprising bismuth, indium, tin, or alloysthereof. Unreflowed bond ball 238 is may be a high melting point solderball such a solder ball made of a lead-tin alloy and may beapproximately three-hundred microns in diameter.

To make mechanical and electrical contact between bond pad 234 andprinted circuit board interconnect 245, the structure shown in FIG. 11is heated by reflow control circuits (not shown) and logic gates (notshown) in FPGA dice (not shown) disposed on semiconductor substrate 40.After heating, solder ball 238 and low melting point metal will havejoined to create a solder mass of low temperature eutectic alloy. Thisjoining mechanically and electrically connects interconnects 231 and 245of semiconductor substrate 40 and PCB 50, respectively. Upon subsequentheatings, initiated by reflow control circuits (not shown) of thestructure of FIG. 11 the low temperature alloy formed by solder ball 238and low melting point metal layer 240 melts and remains liquid until thealloy cools below the eutectic temperature and the compositionsolidifies. These heating and cooling cycles may remove voids formed bythermal fatigue and grain grown and improve the electrical andmechanical connections between semiconductor substrate 40 and PCB 50.

FIG. 12 is a cross-sectional diagram showing of solder ball 238, aprinted circuit board interconnect 235, and a low melting point layer240, and a barrier metal layer. FIG. 12 also includes a semiconductorsubstrate 40, semiconductor substrate interconnect 231, passivationlayer 232 and bond pad 234. Semiconductor substrate interconnect 231 isa metal interconnect that may include copper. Low melting point metallayer 240 is a metal or metal alloy selected from a group comprisingbismuth, indium, tin, or alloys thereof. Bond ball 238 may be made of alead-tin alloy and may be approximately three-hundred microns indiameter. Barrier metal layer 246 may be a thin layer of metal such asnickel, and prevents low melting point metal layer 240 from beingabsorbed by solder ball 238. In one embodiment, barrier metal layer 246may be a layer of nickel metal with a thickness of fifty microinches. Inanother embodiment the barrier metal layer may be gold. Barrier metallayer 246 may be deposited onto solder ball 238 by a masking anddeposition processing, or by radio frequency evaporation, e-beamevaporation, electroplating, electroless plating, injection molded or byother processing methods.

To make mechanical and electrical contact between bond bad 234 andprinted circuit board interconnect 245, the structure shown in FIG. 11is heated by reflow control circuits (not shown) and logic gates (notshown) in FPGA dice (not shown) disposed on semiconductor substrate 40.After heating, low melting point metal layer 240 melts and may removeany voids, grain growth and mechanical stress present as a result ofthermal fatigue.

FIG. 13 is a cross-sectional diagram showing a semiconductor substrate40, FPGA integrated circuit dice 41, 42 with reflow control circuits,and a Printed Circuit Board “PCB” 215 wherein the PCB 215 has wells 217for receiving bond balls in accordance with another novel aspect. FPGAintegrated circuit dice 41, 42 are shown disposed on a top surface ofsemiconductor substrate 40. Memory dice 74 and 78 are also showndisposed on semiconductor substrate 40. Arrays of bond bumps 45 areshown disposed between both the FPGA and memory integrated circuits andsemiconductor substrate 40. FPGA dice 41,42 and memory die 74, 78 aremechanically and electrically attached to semiconductor substrate 40 byarrays of bond bumps 45. An array of low temperature bond balls 210 arealso shown disposed between the semiconductor substrate 40 and PCB 215and bond balls 210 electrically and mechanically connect semiconductorsubstrate 40 to PCB 215. Fiber-optic connectors 151 and 152 and othercomponents (not shown) are mounted onto the top surface of PCB 215 andmake connections to circuits in memory dice 74, 78 and FPGA dice 41, 42by interconnect lines in the PCB 215 (not shown) bond balls 210,interconnect within semiconductor substrate 40 (not shown) and arrays ofbond bumps 45. PCB 215 may also contain alignment structures 208, 209that are used to ensure proper electrical and mechanical contact afterbond balls 210 have been melted.

FIG. 13 also shows an array of bond ball wells 217 in PCB 215. Bond ballwells 217 extend into printed circuit board 215 and are aligned witheach bond ball 210 of semiconductor substrate 40. For a 300 micron bondball, a bond ball well of well depth 200 microns may be used. The bondball well may be made by etching or drilling PCB 215. PCB interconnectmetal 213 is present on the bottom surface of each bond ball well 217and is connected to interconnect lines (not shown) within PCB 215. A lowmelting point metal layer 214 is shown disposed within bond ball well217; low melting point metal layer 212 is a metal selected from a groupcomprising bismuth, indium, tin, or alloys thereof.

In the system shown in FIG. 13, FPGA dice 41, 42 contain reflow circuits(not shown) that cause power dissipation in each respective FPGA die.The temperature increase is sufficient to raise semiconductor substrate40, array of bond balls 210, and low melting point metal layer 214 abovethe eutectic temperature of low melting point metal layer 214. Lowmelting point metal layer 214 liquefies and may remove voids present inthe metal prior to liquefaction. Bond ball well 217 contains the liquidmetal and prevents flow of metal away from bond ball well 217. In otherembodiments, the bond ball 211 may include a low temperature metal.

FIG. 14 is a flowchart of a novel method 300. In a first step (step301), a device is operated. The device includes a circuit board (forexample, PCB 50 of FIG. 5), an integrated circuit (for example, FPGA die41 of FIG. 5), and a plurality of low temperature bond balls (forexample, bond balls 72 of FIG. 5). The bond balls are coupled to thecircuit board. The logic gates are part of the integrated circuit.

In a second step (step 302), power dissipation of the logic gates isincreased such that the bond balls melt. In one example, powerdissipation is increased by loading a particular bit stream into theFPGA.

In a third step (step 303), the temperature of the device is reducedsuch that the bond balls solidify. In one example, the temperature isreduced by loading a different bit stream into the FPGA.

In a fourth step (step 304), operating the device with the bond ballsbeing solid. In one example, the FPGA is operated using the differentbit stream such that the temperature is below the melting point of thebond balls.

Although certain specific embodiments are described above forinstructional purposes, the teachings of this patent document havegeneral applicability and are not limited to the specific embodimentsdescribed above. Accordingly, various modifications, adaptations, andcombinations of various features of the described embodiments can bepracticed without departing from the scope of the invention as set forthin the claims.

1-17. (canceled)
 18. A method comprising: (a) supplying a firstbit-stream for a Field Programmable Gate Array (FPGA), wherein the firstbit-stream is adapted to configure the FPGA to increase a powerdissipation of a plurality of logic gates of the FPGA such that atemperature of a device is increased thereby melting a plurality of bondballs, wherein the device comprises the FPGA and the plurality of bondballs.
 19. The method of claim 18, further comprising: (b) supplying asecond bit-stream for the FPGA, wherein the second bit-stream is adaptedto configure the FPGA to detect defects, and wherein the firstbit-stream is adapted to be loaded into the FPGA in response to adetection of a defect by the FPGA when the FPGA is configured by thesecond bit-stream.
 20. The method of claim 19, wherein the supplying of(a) and the supplying of (b) occur by supplying the device, and whereinthe first and second bit-streams are stored in a memory in the device.21. The method of claim 18, wherein the FPGA comprises a reflow controlcircuit, and wherein the power dissipation is increased by the reflowcontrol circuit.
 22. The method of claim 18, further comprising: (c)detecting a temperature, wherein the power dissipation is increasedbased on the detecting of the temperature.
 23. The method of claim 22,wherein the power dissipation of the plurality of logic gates isincreased such that the temperature of the FPGA is increased greaterthan 0.5 degrees Centigrade per second.
 24. The method of claim 18,wherein after the power dissipation is increased and the temperature ofthe device is increased, the temperature of the device is reduced suchthat the plurality of bond balls solidify.
 25. The method of claim 19,further comprising: (c) operating the FPGA after the plurality of bondballs solidify and after the FPGA is configured by the secondbit-stream.
 26. The method of claim 18, wherein the power dissipation isincreased by increasing a clock rate.
 27. The method of claim 18,wherein the plurality of bond balls comprise indium.
 28. The method ofclaim 18, wherein the plurality of bond balls couples a semiconductorsubstrate to a circuit board, wherein a plurality of bond bumps couplesthe semiconductor substrate to the FPGA, and wherein the circuit boardand the semiconductor substrate have disparate coefficients of linearthermal expansion.
 29. A method comprising: (a) operating a devicecomprising a Field Programmable Gate Array (FPGA), a semiconductorsubstrate, a circuit board, a plurality of bond bumps and a plurality ofbond balls, wherein the bond bumps are disposed between the FPGA and thesemiconductor substrate, wherein the bond balls are disposed between thesemiconductor substrate and the circuit board, wherein the FPGA includeslogic gates, and wherein the device is operated such that the logicgates have a power dissipation that maintains a temperature of thedevice such that the bond balls remain solid; and (b) supplying abit-stream for the FPGA that configures the FPGA to increase the powerdissipation of the logic gates such that the temperature of the deviceis increased and melts the bond balls.
 30. The method of claim 29,wherein the bit-stream configures a reflow control circuit in the FPGA,and wherein the increasing the power dissipation is performed by thereflow control circuit.
 31. The method of claim 29, further comprising:(c) detecting a temperature, wherein the power dissipation is increasedbased on the detecting of the temperature.
 32. The method of claim 29,wherein the power dissipation of the logic gates is increased such thatthe temperature of the device is increased greater than 0.5 degreesCentigrade per second.
 33. The method of claim 29, wherein after thepower dissipation is increased and the temperature of the device isincreased, the temperature of the device is reduced such that the bondballs solidify.
 34. The method of claim 29, further comprising: (c)operating the device after the bond balls solidify and after the FPGA isconfigured by the bit-stream.
 35. The method of claim 29, wherein thepower dissipation is increased by increasing a clock rate.
 36. Themethod of claim 29, wherein the bond balls comprise indium.
 37. Themethod of claim 29, wherein the circuit board and the semiconductorsubstrate have disparate coefficients of linear thermal expansion.